Datasheet AT89S53 (Microchip) - 4

Some Port 1 pins provide additional functions. P1.0 and Port 3 pins that are externally being pulled low will source P1.1 can be configured to be the timer/counter 2 external current (I ) because of the pullups. IL count input (P1.0/T2) and the timer/counter 2 trigger input Port 3 also serves the functions of various special features (P1.1/T2EX), respectively. of the AT89S53, as shown in the following table. Port 3 also receives some control signals for Flash pro-
Pin Description
gramming and verification. Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift
Port Pin Alternate Functions
clock input/output pins as shown in the following table. P3.0 RXD (serial input port) P3.1 TXD (serial output port)
Port Pin Alternate Functions
P3.2 INT0 (external interrupt 0) P1.0 T2 (external count input to Timer/Counter 2), clock-out P3.3 INT1 (external interrupt 1) P1.1 T2EX (Timer/Counter 2 capture/reload trigger P3.4 T0 (timer 0 external input) and direction control) P3.5 T1 (timer 1 external input) P1.4 SS (Slave port select input) P3.6 WR (external data memory write strobe) P1.5 MOSI (Master data output, slave data input pin P3.7 RD (external data memory read strobe) for SPI channel) P1.6 MISO (Master data input, slave data output pin
RST
for SPI channel) Reset input. A high on this pin for two machine cycles while P1.7 SCK (Master clock output, slave clock input pin the oscillator is running resets the device. for SPI channel)
ALE/PROG
Port 1 also receives the low-order address bytes during Address Latch Enable is an output pulse for latching the Flash programming and verification. low byte of the address during accesses to external mem- ory. This pin is also the program pulse input (PROG) during
Port 2
Flash programming. Port 2 is an 8-bit bidirectional I/O port with internal pullups. In normal operation, ALE is emitted at a constant rate of 1/6 The Port 2 output buffers can sink/source four TTL inputs. the oscillator frequency and may be used for external tim- When 1s are written to Port 2 pins, they are pulled high by ing or clocking purposes. Note, however, that one ALE the internal pullups and can be used as inputs. As inputs, pulse is skipped during each access to external data Port 2 pins that are externally being pulled low will source memory. current (I ) because of the internal pullups. IL If desired, ALE operation can be disabled by setting bit 0 of Port 2 emits the high-order address byte during fetches SFR location 8EH. With the bit set, ALE is active only dur- from external program memory and during accesses to ing a MOVX or MOVC instruction. Otherwise, the pin is external data memory that use 16-bit addresses (MOVX @ weakly pulled high. Setting the ALE-disable bit has no DPTR). In this application, Port 2 uses strong internal pul- effect if the microcontroller is in external execution mode. lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some
PSEN
control signals during Flash programming and verification. Program Store Enable is the read strobe to external pro- gram memory.
Port 3
When the AT89S53 is executing code from external pro- Port 3 is an 8 bit bidirectional I/O port with internal pullups. gram memory, PSEN is activated twice each machine The Port 3 output buffers can sink/source four TTL inputs. cycle, except that two PSEN activations are skipped during When 1s are written to Port 3 pins, they are pulled high by each access to external data memory. the internal pullups and can be used as inputs. As inputs,
4 AT89S53
0787E–MICRO–3/06 Document Outline Block Diagram Instruction Set Features Description Pin Description VCC GND Port 0 Port 1 Pin Description Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Special Function Registers Data Memory - RAM Programmable Watchdog Timer Timer 0 and 1 Timer 2 Capture Mode Auto-reload (Up or Down Counter) Baud Rate Generator Programmable Clock Out UART Serial Peripheral Interface Interrupts Oscillator Characteristics Idle Mode Status of External Pins During Idle and Power-down Modes Power-down Mode Program Memory Lock Bits Lock Bit Protection Modes(1)(2) Programming the Flash Programming Interface Serial Downloading Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The max... Serial Programming Algorithm Serial Programming Instruction Flash Parallel Programming Modes Flash Programming and Verification Characteristics - Parallel Mode Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information Pin Configurations