Datasheet AT89S53 (Microchip) - 5
| Manufacturer | Microchip |
| Description | 8-bit Microcontroller with 12K Bytes Flash |
| Pages / Page | 35 / 5 — AT89S53. EA/VPP. XTAL1. XTAL2. Table 1 |
| File Format / Size | PDF / 892 Kb |
| Document Language | English |
AT89S53. EA/VPP. XTAL1. XTAL2. Table 1
Model Line for this Datasheet
Text Version of Document
AT89S53 EA/VPP
enable voltage (V ) during Flash programming when 12- PP External Access Enable. EA must be strapped to GND in volt programming is selected. order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH.
XTAL1
Note, however, that if lock bit 1 is programmed, EA will be Input to the inverting oscillator amplifier and input to the internally latched on reset. internal clock operating circuit. EA should be strapped to V for internal program execu- CC tions. This pin also receives the 12-volt programming
XTAL2
Output from the inverting oscillator amplifier.
Table 1.
AT89S53 SFR Map and Reset Values 0F8H 0FFH B 0F0H 0F7H 00000000 0E8H 0EFH ACC 0E0H 0E7H 00000000 0D8H 0DFH PSW SPCR 0D0H 0D7H 00000000 000001XX T2CON T2MOD RCAP2L RCAP2H TL2 TH2 0C8H 0CFH 00000000 XXXXXX00 00000000 00000000 00000000 00000000 0C0H 0C7H IP 0B8H 0BFH XX000000 P3 0B0H 0B7H 11111111 IE SPSR 0A8H 0AFH 0X000000 00XXXXXX P2 0A0H 0A7H 11111111 SCON SBUF 98H 9FH 00000000 XXXXXXXX P1 WCON 90H 97H 11111111 00000010 TCON TMOD TL0 TL1 TH0 TH1 88H 8FH 00000000 00000000 00000000 00000000 00000000 00000000 P0 SP DP0L DP0H DP1L DP1H SPDR PCON 80H 87H 11111111 00000111 00000000 00000000 00000000 00000000 XXXXXXXX 0XXX0000
5
0787E–MICRO–3/06 Document Outline Block Diagram Instruction Set Features Description Pin Description VCC GND Port 0 Port 1 Pin Description Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Special Function Registers Data Memory - RAM Programmable Watchdog Timer Timer 0 and 1 Timer 2 Capture Mode Auto-reload (Up or Down Counter) Baud Rate Generator Programmable Clock Out UART Serial Peripheral Interface Interrupts Oscillator Characteristics Idle Mode Status of External Pins During Idle and Power-down Modes Power-down Mode Program Memory Lock Bits Lock Bit Protection Modes(1)(2) Programming the Flash Programming Interface Serial Downloading Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The max... Serial Programming Algorithm Serial Programming Instruction Flash Parallel Programming Modes Flash Programming and Verification Characteristics - Parallel Mode Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information Pin Configurations
enable voltage (V ) during Flash programming when 12- PP External Access Enable. EA must be strapped to GND in volt programming is selected. order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH.
XTAL1
Note, however, that if lock bit 1 is programmed, EA will be Input to the inverting oscillator amplifier and input to the internally latched on reset. internal clock operating circuit. EA should be strapped to V for internal program execu- CC tions. This pin also receives the 12-volt programming
XTAL2
Output from the inverting oscillator amplifier.
Table 1.
AT89S53 SFR Map and Reset Values 0F8H 0FFH B 0F0H 0F7H 00000000 0E8H 0EFH ACC 0E0H 0E7H 00000000 0D8H 0DFH PSW SPCR 0D0H 0D7H 00000000 000001XX T2CON T2MOD RCAP2L RCAP2H TL2 TH2 0C8H 0CFH 00000000 XXXXXX00 00000000 00000000 00000000 00000000 0C0H 0C7H IP 0B8H 0BFH XX000000 P3 0B0H 0B7H 11111111 IE SPSR 0A8H 0AFH 0X000000 00XXXXXX P2 0A0H 0A7H 11111111 SCON SBUF 98H 9FH 00000000 XXXXXXXX P1 WCON 90H 97H 11111111 00000010 TCON TMOD TL0 TL1 TH0 TH1 88H 8FH 00000000 00000000 00000000 00000000 00000000 00000000 P0 SP DP0L DP0H DP1L DP1H SPDR PCON 80H 87H 11111111 00000111 00000000 00000000 00000000 00000000 XXXXXXXX 0XXX0000
5
0787E–MICRO–3/06 Document Outline Block Diagram Instruction Set Features Description Pin Description VCC GND Port 0 Port 1 Pin Description Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Special Function Registers Data Memory - RAM Programmable Watchdog Timer Timer 0 and 1 Timer 2 Capture Mode Auto-reload (Up or Down Counter) Baud Rate Generator Programmable Clock Out UART Serial Peripheral Interface Interrupts Oscillator Characteristics Idle Mode Status of External Pins During Idle and Power-down Modes Power-down Mode Program Memory Lock Bits Lock Bit Protection Modes(1)(2) Programming the Flash Programming Interface Serial Downloading Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The max... Serial Programming Algorithm Serial Programming Instruction Flash Parallel Programming Modes Flash Programming and Verification Characteristics - Parallel Mode Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information Pin Configurations
