Datasheet AD8065, AD8066 (Analog Devices) - 9

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Data Sheet AD8065/AD8066 ABSOLUTE MAXIMUM RATINGS Table 4.
RMS output voltages should be considered. If RL is referenced to
Parameter Rating
VS−, as in single-supply operation, then the total drive power is Supply Voltage 26.4 V VS × IOUT. Power Dissipation See Figure 3 If the rms signal levels are indeterminate, then consider the Common-Mode Input Voltage VEE − 0.5 V to VCC + 0.5 V worst case, when VOUT = VS/4 for RL to midsupply. Differential Input Voltage 1.8 V V 2 4 / Storage Temperature Range −65°C to +125°C = × + D P ( SV IS) ( S ) Operating Temperature Range −40°C to +85°C RL AD8065WARTZ Only −40°C to +105°C In single-supply operation with RL referenced to VS−, worst case Lead Temperature 300°C is VOUT = VS/2. (Soldering, 10 sec)
2.0
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these
1.5
or any other conditions above those indicated in the operational
MSOP-8
section of this specification is not implied. Operation beyond
SOIC-8
the maximum operating conditions for extended periods may
1.0
affect product reliability.
SOT-23-5 MAXIMUM POWER DISSIPATION 0.5
The maximum safe power dissipation in the AD8065/AD8066
MAXIMUM POWER DISSIPATION (W)
packages is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches
0
the junction temperature. At approximately 150°C, which is the
–60 –40 –20 0 20 40 60 80 100
glass transition temperature, the plastic changes its properties.
AMBIENT TEMPERATURE (°C)
02916-E-003 Even temporarily exceeding this temperature limit can change Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board the stresses that the package exerts on the die, permanently Airflow increases heat dissipation, effectively reducing θJA. Also, shifting the parametric performance of the AD8065/AD8066. more metal directly in contact with the package leads from Exceeding a junction temperature of 175°C for an extended metal traces, through holes, ground, and power planes reduce time can result in changes in the silicon devices, potentially the θJA. Care must be taken to minimize parasitic capacitances causing failure. at the input leads of high speed op amps as discussed in the The still air thermal properties of the package and PCB (θ Layout, Grounding, and Bypassing Considerations section. JA), ambient temperature (TA), and total power dissipated in the Figure 3 shows the maximum safe power dissipation in the package (PD) determine the junction temperature of the die. package vs. the ambient temperature for the SOIC (125°C/W), The junction temperature can be calculated by SOT-23 (180°C/W), and MSOP (150°C/W) packages on a T JEDEC standard 4-layer board. θJA values are approximations. J = TA + (PD × θJA) The power dissipated in the package (P
OUTPUT SHORT CIRCUIT
D) is the sum of the quiescent power dissipation and the power dissipated in the Shorting the output to ground or drawing excessive current for package due to the load drive for al outputs. The quiescent the AD8065/AD8066 wil likely cause catastrophic failure. power is the voltage between the supply pins (VS) times the quiescent current (I S). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS /2 × IOUT, some of
ESD CAUTION
which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. P = + − D Quiescent Power (Total Drive Power Load Power)  V V  V 2 = × +  ×  − D P ( SV IS) S OUT OUT  2 RL  RL Rev. L | Page 9 of 28 Document Outline Features Applications Connection Diagrams General Description Table of Contents Revision History Specifications ±5 V Specifications ±12 V Specifications +5 V Absolute Maximum Ratings Maximum Power Dissipation Output Short Circuit ESD Caution Typical Performance Characteristics Test Circuits SOIC-8 Pinout Theory of Operation Closed-Loop Frequency Response Noninverting Closed-Loop Frequency Response Inverting Closed-Loop Frequency Response Wideband Operation Input Protection Thermal Considerations Input and Output Overload Behavior Layout, Grounding, and Bypassing Considerations Power Supply Bypassing Grounding Leakage Currents Input Capacitance Output Capacitance Input-to-Output Coupling Wideband Photodiode Preamp High Speed JFET Input Instrumentation Amplifier Video Buffer Outline Dimensions Ordering Guide Automotive Products