Marián Štofka EDN Using a shift register with parallel output is a common way to design a pulse generator with N inputs and pulsed outputs having a width of T/N. To keep the output pulses consecutive, you can use feedback from the last output to the first input. At poweron, such a circuit can have a random combination of logic zeros and ones, forming an undesired data content of the shift register. To avoid circulating undesired states and to enter a proper sequence, you need a special feedback. The circuit in Figure 1 is a threestage shift register that uses Dtype flipflops. It has three outputs, Q_{1}, Q_{2}, and Q_{3}, each of which produces a periodic pulse having a width of T_{REP}/3. T_{REP} = 3T_{CLK} is the period at which the sequence repeats at any of the three outputs. A twoinput NOR gate creates the feedback. The gate’s D_{1} output connects to the D input of flipflop FF_{1}, and its inputs connect to Q_{1} and Q_{2}. A logicone bit at D_{1} means that, at the nearest lowtohigh transition of the clock, this signal will place a logic one at output Q_{1}.
You can interpret this feedback in words by writing a logic zero into FF_{1} at the nearest lowtohigh transition of the clock signal, if at least one of the Q_{1} or Q_{2} outputs has a logicone state. You write a logic one into FF_{1} if both the Q_{1} and the Q_{2} outputs are at logic zero. This feedback adds a selfcorrecting feature, which is illustrated by the assumption that the initial state of the circuit is intentionally undesired. Using this result, the following sequences illustrate state correction, in which the logical states in the bit triads correspond left to right to Q_{1}, Q_{2}, and Q_{3}: 111→011→001→100→010→001 From this example, you can see that erroneous state 111 selfcorrects within two periods of the clock. For the undesired 000 state, the proper cycling enters at the nearest lowtohigh transition of the clock signal.
You can determine the upper limit of the clock frequency from an assumption of the gate output, which changes after a lowtohigh transition of the clock. This condition must be ready with a setup time, T_{SETUP}, the next time the clock transitions from low to high (Figure 2). Thus, T_{CLKMIN} = T_{PQHL} + T_{PGLH} + T_{SETUP}, where T_{PQHL} and T_{PGLH} are signalpropagation delays of the flipflop and the gate, respectively, at the respective outputlevel transition. By using the worstcase values of propagation delays from the devices’ data sheets, you get a minimum clock period of 4.4 nsec for a supply voltage of 1.8 V and a minimum clock period of 3.5 nsec for a supply voltage of 2.5 V. As the 3.5nsec value gives a clock frequency higher than the guaranteed toggle frequency for the flipflop, you should accept the maximum clock frequency at 275 MHz for a supply voltage of 2.5 V. For a supply voltage of 1.8 V, the maximum clock frequency should be 227 MHz. The maximum repetition rate of signals at Q_{1}, Q_{2}, and Q_{3} outputs is the maximum clock frequency divided by three, or 75.6 MHz. Materials on the topic 

