Datasheet ADIS16201 (Analog Devices) - 27

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ADIS16201 Data Sheet Table 28. COMMAND Bit Descriptions
The data-ready hardware I/O pin is reset automatical y to an
Bit Description
inactive state part way through the next conversion cycle, 15:8 Not used. resulting in a pulse train with a duty cycle varying from ~15% 7 Software Reset Command. Allows for resetting of the to 35%, depending upon the sample period setting. Upon device via the SPI. completion of the next sample/conversion/processing cycle, the 6:4 Not used. data ready hardware I/O line is reasserted. 3 Manual Flash Update Command. This command is utilized in updating all of the nonvolatile registers to The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control flash. Once the command is initiated, the supply registers can influence the same GPIO pins. A priority level has voltage, VDD, must remain within specified limits for been established to avoid conflicting assignments of the two 50 ms to assure proper update of the nonvolatile GPIO pins. This priority level is defined as MSC_CTRL and has registers to flash. precedence over ALM_CTRL, which has precedence over 2 Auxiliary DAC Latch Command. This command acts to GPIO_CTRL. latch the AUX_DAC control register data into the auxiliary DAC upon receipt of the command. This allows The self-test enable bit al ows the user to place the ADIS16201 for sequential loading of the upper and lower AUX_DAC data bytes via the SPI without having the auxiliary DAC into a diagnostics mode for purposes of verifying the base transition into unwanted, intermediate states based sensor’s operation. When this bit is set high, an electrostatic upon the individual AUX_DAC data bytes. Once the two force is generated internally to the sensor. The resulting bytes of AUX_DAC are loaded, the DAC latch command movement within the sensor al ows the end user to test if the is initiated to move the data into the auxiliary DAC itself. accelerometer is functional. Typical change in the output is 1 Factory Reset Command. Allows the user to reset all 328 mg (corresponding to 708 LSB). Once the self-test enable four system level offset registers and all four system bit is returned to a low state, normal operation is resumed. level scale registers to the nominal settings (000h and 800h, respectively) upon receipt of command. Data
MSC_CTRL Register Definition
within the moving average filters will likewise be reset. As the manual flash command identified below, this
Address Default1 Format Access
command stores all of the nonvolatile registers to flash. 0x35, 0x34 0x0000 N/A R/W Once the command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to assure 1 Default is valid only until the first register write cycle. proper update of the nonvolatile registers to flash. The 16-bit miscellaneous control register is used in the 0 Null Command. Loads the X/Y inclination offset as well control ing of the self-test and data-ready hardware functions. as the X/Y acceleration offset registers with values that This includes turning on and off the self-test function, as well as zero out the inclination and acceleration outputs. enabling and configuring the data-ready function. For the data- Useful as a single command to simultaneously zero both inclination and acceleration outputs. As the ready function, the written values are nonvolatile, allowing for manual flash command identified below, this command data recovery upon reset. The self-test data is volatile and is set stores all of the nonvolatile registers to flash. Once the to 0s upon reset. This register has read/write capability. command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to assure
Table 29. MSC_CTRL Bit Descriptions
proper update of the nonvolatile registers to flash.
Bit Description
15:9 Not used.
MISCELLANEOUS CONTROL REGISTER
8 Self-test enable. The MSC_CTRL control register within the ADIS16201 1: ST enabled provides control of two miscel aneous functions: the data-ready 0: ST disabled hardware I/O function and the self-test function. The bits to 7:3 Not used. control these two functions are shown in Table 29. 2 Data-ready enable. The operation of the data-ready hardware I/O function is very 1: DR enabled similar to the alarm hardware I/O function (controlled through 0: DR disabled the ALM_CTRL control register). In this case, the MSC_CNTRL 1 Data-ready polarity. register can be used in setting up one of the two GPIO pins to 1: Active high serve as the hardware output pin that indicates when the 0: Active low sampling, conversion, and processing of the seven data output 0 Data-ready line select. variables has been completed. This register provides the ability 1: DIO1 to enable the data-ready hardware function and establish its 0: DIO0 polarity. Rev. C | Page 26 of 32 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Accelerometer Operation Inclinometer Operation Temperature Sensor Basic Operation Data Output Register Access Programming and Control Control Register Overview Control Register Access Control Register Details Calibration Calibration Register Definitions XACCL_OFF Register Definition XACCL_SCALE Register Definition YACCL_OFF Register Definition YACCL_SCALE Register Definition XINCL_OFF Register Definition XINCL_SCALE Register Definition YINCL_OFF Register Definition YINCL_SCALE Register Definition Alarms ALM_MAG1 Register Definition ALM_SMPL1 Register Definition ALM_MAG2 Register Definition ALM_SMPL2 Register Definition ALM_CTRL Register Definition Sample Period Control SMPL_PRD Register Definition Filtering Control AVG_CNT Register Definition Power-Down Control PWR_MDE Register Definition Status Feedback STATUS Register Definition Command Control COMMAND Register Definition Miscellaneous Control Register MSC_CTRL Register Definition Peripherals Auxiliary ADC Function Auxiliary DAC Function AUX_DAC Register Definition General Purpose I/O Control GPIO_CTRL Register Definition Applications Serial Peripheral Interface (SPI) Hardware Considerations Grounding and Board Layout Recomendations Bandgap Reference Power-On Reset Operation Second-Level Assembly Example Pad Layout Outline Dimensions Ordering Guide