Datasheet AT89S53 (Microchip) - 2

Pin Configurations
PDIP PLCC (T2) P1.0 1 40 VCC (T2 EX) P1.1 2 39 P0.0 (AD0) P1.2 3 38 P0.1 (AD1) P1.3 4 37 P0.2 (AD2) P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) (SS) P1.4 5 36 P0.3 (AD3) 6 5 4 3 2 1 (MOSI) P1.5 6 35 P0.4 (AD4) 44 43 42 41 40 (MOSI) P1.5 7 39 P0.4 (AD4) (MISO) P1.6 7 34 P0.5 (AD5) (MISO) P1.6 8 38 P0.5 (AD5) (SCK) P1.7 8 33 P0.6 (AD6) (SCK) P1.7 9 37 P0.6 (AD6) RST 9 32 P0.7 (AD7) RST 10 36 P0.7 (AD7) (RXD) P3.0 10 31 EA/VPP (RXD) P3.0 11 35 EA/VPP (TXD) P3.1 11 30 ALE/PROG NC 12 34 NC (INT0) P3.2 12 29 PSEN (TXD) P3.1 13 33 ALE/PROG (INT1) P3.3 13 28 P2.7 (A15) (INT0) P3.2 14 32 PSEN (T0) P3.4 14 27 P2.6 (A14) (INT1) P3.3 15 31 P2.7 (A15) (T1) P3.5 15 26 P2.5 (A13) (T0) P3.4 16 30 P2.6 (A14) (WR) P3.6 16 25 P2.4 (A12) (T1) P3.5 17 29 P2.5 (A13) (RD) P3.7 17 24 P2.3 (A11) 18 19 20 21 22 23 24 25 26 27 28 XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) NC GND 20 21 P2.0 (A8) GND XTAL2 XTAL1 (WR) P3.6 (RD) P3.7 (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 TQFP P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) 44 43 42 41 40 39 38 37 36 35 34 (MOSI) P1.5 1 33 P0.4 (AD4) (MISO) P1.6 2 32 P0.5 (AD5) (SCK) P1.7 3 31 P0.6 (AD6) RST 4 30 P0.7 (AD7) (RXD) P3.0 5 29 EA/VPP NC 6 28 NC (TXD) P3.1 7 27 ALE/PROG (INT0) P3.2 8 26 PSEN (INT1) P3.3 9 25 P2.7 (A15) (T0) P3.4 10 24 P2.6 (A14) (T1) P3.5 11 23 P2.5 (A13) 12 13 14 15 16 17 18 19 20 21 22 GND GND XTAL2 XTAL1 (WR) P3.6 (RD) P3.7 (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
Pin Description
Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external program and data memory. In this mode, P0 has internal
VCC
pullups. Supply voltage. Port 0 also receives the code bytes during Flash program- m i n g a n d o u t p u t s t h e c o d e b y t e s d u r i n g p r o g r a m
GND
verification. External pullups are required during program Ground. verification.
Port 0 Port 1
Port 0 is an 8-bit open drain bidirectional I/O port. As an Port 1 is an 8-bit bidirectional I/O port with internal pullups. output port, each pin can sink eight TTL inputs. When 1s The Port 1 output buffers can sink/source four TTL inputs. are written to port 0 pins, the pins can be used as high- When 1s are written to Port 1 pins, they are pulled high by impedance inputs. the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I ) because of the internal pullups. IL
2 AT89S53
0787E–MICRO–3/06 Document Outline Block Diagram Instruction Set Features Description Pin Description VCC GND Port 0 Port 1 Pin Description Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Special Function Registers Data Memory - RAM Programmable Watchdog Timer Timer 0 and 1 Timer 2 Capture Mode Auto-reload (Up or Down Counter) Baud Rate Generator Programmable Clock Out UART Serial Peripheral Interface Interrupts Oscillator Characteristics Idle Mode Status of External Pins During Idle and Power-down Modes Power-down Mode Program Memory Lock Bits Lock Bit Protection Modes(1)(2) Programming the Flash Programming Interface Serial Downloading Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The max... Serial Programming Algorithm Serial Programming Instruction Flash Parallel Programming Modes Flash Programming and Verification Characteristics - Parallel Mode Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information Pin Configurations