Simplified topology of logic gates comprising voltage inverter, showing driver device (U1), switch device (U2), and coupling (CC), pump (CP), and filter (CF) capacitors
| Authors | Stephen Woodward |
| Main Document | Article «Voltage inverter uses gate's output pins as inputs and its ground pin as output» |
| Description | Figure 2 |
| File Format / Size | PDF / 9 Kb |
| Document Language | English |
Other Materials from the Main Document
- Article «Voltage inverter uses gate's output pins as inputs and its ground pin as output»
- Figure 1. Simplified schema of typical basic CMOS gate I/O circuitry showing clamping diodes and complementary FET switch pair
- Figure 2. Simplified topology of logic gates comprising voltage inverter, showing driver device (U1), switch device (U2), and coupling (CC), pump (CP), and filter (CF) capacitors
- Figure 3. Complete voltage inverter: 100 kHz pump clock (set by R1C1), Schmidt trigger and driver (U1), and commutator (U2)
