Jean-Bernard Guiot
EDN
Computers find universal use in industrial-control systems. During power- and start-up sequences (booting), the outputs of such control systems may yield uncontrolled pulses before the software defines the correct status. If these outputs control the power-on state of a system, these uncontrolled pulses could have dramatic consequences. Safety regulations forbid such erratic behavior. The circuit in Figure 1 is a cost-effective approach to the spurious-pulse problem. The circuit costs approximately 10 times less than other available timers. The open-collector output of the controlling device connects to the reset input of the CD4060 counter, IC1. You can easily adapt this circuit to other controller-output configurations, such as an optocoupler. As long as R1 pulls the reset input high (controller-output off), the counter's clock stays disabled and all outputs are low. C, R2, and R3 are the timing components for IC1. With R2 = R3 = 10 kΩ and C = 0.1 µF, the measured clock frequency is approximately 360 Hz.
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| Figure 1. | This simple timing circuit ensures that a controller’s spurious pulses do not affect a system’s start-up operation. |
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The output of the circuit is Q12. The reset input must stay low longer than
for the output to turn on (n is the output number, 12). Any spurious pulse from the controller's output that is shorter than 5 sec has no effect on the output of the circuit. Output Q13 of the counter turns on after 11 sec, Q14 after 23 sec, and so on. The LED, connected to Q7 through R4, flashes during the timing period. With VCC = 12 V and an LED current of 10 mA,
For safety reasons, you can add the optocoupler, IC2. If output Q12 of the counter fails (shorted to VCC), the output turns on only if the controller's output is on. Choose the value of R1 depending on the controller's output and the noise level; in this design, R1 = 10 kΩ. Note that VCC should have a maximum value of 15 V for the CD4060 and 6 V for the 74HC4060.
