Rex Niven
EDN
The ubiquitous LCD (Figure 1) (and VFD) modules based on the HD44780 controller IC can require up to 12 lines from the host.
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| Figure 1. | A typical LCD module. | |
This hardware interface Design Idea (Figure 2) reduces the connection to just one wire, allowing a basic microcontroller with limited I/O to drive a large display, either directly, through a standard interface, or even an opto-isolator.
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| Figure 2. | One-wire LCD interface schematic. | |
The LCD’s eight data-bit inputs are encoded by a sequence of short and long pulses clocking a serial-to-parallel shift register, with control and data signals generated by a pair of dual monostables. The RS signal is controlled by leaving the serial line low or high after the eight data bits are sent. The read function of the display is dispensed with (R/W is tied low), so status can’t be read, meaning the module’s processing delays (up to several milliseconds) must be accommodated by software timing alone.
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| Figure 3. | Timing diagram. | |
Each byte needs to be sent as eight bits, MSb first. The firmware timing needs to match the hardware time constants: The bits should be transmitted two delay units apart. The delay SS (Figure 3) should be several delay units. There needs to be a gap between bytes of several bit times to allow the E pulse to finish before changing RS. A delay unit is defined as the monostable period set by R2 & C2, which can range from around 7 µs to 12 µs depending on the particular IC family used.
