The performance of the watchdog circuit in Figure 1 may not match that of a dedicated watchdog circuit, but this circuit is helpful when the only watchdog in the lab doesn’t meet your design’s temperature requirement and when you are in a hurry to finish a prototype.
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| Figure 1. | A charge pump comprising D1, D2, C1, and C2 inhibits a three-gate oscillator when input activity exists. After 40 msec without input activity, the oscillator starts running and produces a reset signal. |
The circuit operates on a simple principle. When digital activity occurs on the input, a charge pump comprising C1, D1, D2, and C2 keeps C2 charged. R1 is the discharge resistor for C2. IC1A detects the charge level through R2. A charged condition inhibits the three-gate oscillator comprising IC1B, IC1C, and IC1D, and the active-high reset-high output stays low.
When the voltage at the input of IC1A drops below the CMOS threshold, the oscillator starts working and produces a square wave. The high time of the reset-high output resets the µP under control, which must start the activity (and activate the watchdog input) before the end of the low time. R3 and C3 essentially control the high and low times, which have almost the same value.
Although this design monitors an RS-232C line, you can use the circuit to monitor a digital level. When monitoring an RS-232C line with the values in Figure 1, the watchdog starts resetting 40 msec after detecting no activity and requires less than 20 msec to inhibit the oscillator after input activity resumes.
