This Design Idea describes a new class of logic gates, which we have named resistor-FET-logic, aka “RFL.” How do we know it is new? While FET switches are common today, we have been unable to find a similar resistor-FET-logic. Further, RTL (resistor-transistor-logic) is defined today as resistor-BJT-logic. BJTs are still de rigueur when discussing transistorized designs, which would not be the case if RFL were a known concept.
How could an entire class of logic gates be overlooked? In the 1960s, things moved quickly from RTL (1961) to DTL (1962) then TTL (1963). While RFL could have been invented from about 1960, it was curiously passed over. RFL would fit the line-up of the more familiar logic classes as follows: DL, RTL, RFL, DTL, TTL, and CMOS. It is not to be confused with NMOS logic, which typically requires two or three times as many FETs to implement an equivalent function.
RFL offers several significant advantages over RTL, and in some cases over CMOS as well. An obvious advantage is that it consumes much less power than RTL (and with that, less space). In addition, the FET core makes it easier to design with than RTL. In addition, RFL can be customized to work with a wide range of supply voltages, input voltages, output currents, and so on.
Figure 1 illustrates how YES, NOT, AND, OR, NAND, and NOR gates are implemented in RFL using a 2N7000 N-channel MOSFET and a 5 V supply. (Note that the XOR and XNOR functions have been omitted here, due to their complexity.)
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| Figure 1. | Basic logic functions implemented in RFL. |
Given that the gate threshold voltage of a 2N7000 MOSFET lies around 1.9 V, the same circuit (Figure 1, left) covers:
- a YES gate (A and B combined, with P1 adjusted to around 30 kΩ)
- an AND gate (P1 adjusted to around 30 kΩ) and
- an OR gate (P1 adjusted to around 160 kΩ).
The inverted circuit (Figure 1, right) similarly covers NOT, NAND, and NOR gates. Fixed resistors may be used in place of P1 if desired. Figure 2 shows a breadboard of the left circuit shown in Figure 1.
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| Figure 2. | A breadboard of the left circuit in Figure 1, which implements YES, AND, and OR gates. |
The Table 1 shows illustrative (not precise) potentials at FET Q1’s gate, and the outputs at terminal Q, whether HIGH or LOW. Note that, if gates are cascaded, input and output impedances may need to be adjusted to give the desired output voltage and current.
| Table 1. | Illustrative (not precise) potentials at FET Q1’s gate, and the outputs at terminal Q, whether HIGH or LOW |
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| FL. = FLOATING GATE THRESHOLD VOLTAGE 1.9 V |
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In the same way that RTL logic gave rise to a profusion of ideas, the possibilities of RFL appear to be too numerous to catalog. However, some possibilities seem worth mentioning. Lower output impedances may be used to power circuits directly. In addition, simple diodes may be used to isolate the inputs from each other.
Depending how RFL gates are used, it may be possible for a design to approach zero current consumption. In some cases, the complementary BS250 P-channel MOSFET may be used to that end, along with the addition of DC blocking capacitors where appropriate. The author has found RFL to be particular usefully for fast digital mixers and charge pumps. It is especially convenient where a single simple gate is required.
