A control loop that produces control voltage of negative polarity for n-channel JFET amplifier in HF and UHF applications
| Authors | Peter Demchenko |
| Main Document | Article «Bias for HF JFET» |
| Description | Figure 2 |
| File Format / Size | PDF / 10 Kb |
| Document Language | English |
Other Materials from the Main Document
- Article «Bias for HF JFET»
- Figure 1. JFETs typically require some reverse bias across the gate terminal and in HF/UHF applications, this is often provided using the voltage across resistor RS
- Figure 2. A control loop that produces control voltage of negative polarity for n-channel JFET amplifier in HF and UHF applications
