The SDD conversion cycle timing for 5 V logic levels
| Authors | Stephen Woodward |
| Main Document | Article «Shannon decoder DAC meets UART» |
| Description | Figure 3 |
| File Format / Size | PDF / 13 Kb |
| Document Language | English |
Other Materials from the Main Document
- Article «Shannon decoder DAC meets UART»
- Figure 1. The Shannon decoder DAC (SDD) concept
- Figure 2. The SDD with 5V asynchronous serial data, similar to a µC UART output
- Figure 3. The SDD conversion cycle timing for 5 V logic levels
- Figure 4. The SDD input modified for RS232 signal levels and polarity
- Figure 5. The SDD analog conversion from RS232 signal levels
