Zuken announces CADSTAR 15.
With high-speed interfaces now almost universal, easing their implementation is vital. CADSTAR’s P.R.Editor now supports impedance balanced routing that simplifies the implementation of high-speed interfaces. Engineers can easily route to JEDEC standards and meet DDR3 performance specifications. This reduces design iterations by helping designers optimize circuits for the highest clock speeds.
«Impedance controlled routing is no longer sufficient. Impedance balanced routing makes it easier for engineers to reduce impedance discontinuities in high-speed manual routing on the same layer, such as lead-in routing specified in JEDEC standard JESD21-C for DDR3 memory», says Jeroen Leinders, CADSTAR Worldwide Sales Manager.
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| CADSTAR is a complete design environment for PCB design – from initial concept through to product realization |
Today’s high-speed channels such as DDRx require ever more sophisticated eye pattern analysis for efficient implementation, considering both base and strobe signals. Improved eye patterns in CADSTAR 15 include automatic measurement of eye height/width and setup/hold.
New features in Power Integrity Advance include adjustable gridding for common-mode voltage maps, decoupling capacitor improvements, and a common user interface for result display in all signal integrity and power integrity analysis tools.
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| Achieve high-speed design requirements with JDEC compliant impedance balanced routing |
Users will appreciate the GUI’s updated appearance with familiar ribbon-style navigation. A new panel for item properties gives modeless (docked, floating or auto-hide) operation in Design Editor and Library Editor. This significantly reduces the number of steps to modify the properties of all item types in the design, and allows multi-item selection and changes – saving time during initial design creation and subsequent edits.
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| Create customized toolbars and macros using the new ribbon-style graphical user interface |
