Freescale Semiconductor launched their QorIQ P3041 communications processors. Key features include a three-level cache hierarchy for optimized latencies, a hardware hypervisor for robust support of multiple operating systems within the device, a trusted boot architecture to ensure code is not tampered with or reverse engineered, efficient data path handling, and improved Serial RapidIO and SATA IP. The P3041 communications processor is scheduled to start sampling in Q4 2010 with qualification planned for 2H 2011.
The P3041 is pin-compatible with Freescale’s QorIQ P4080, P4040, P5020 and P5010 products and shares the same architecture. As a result, products in the P3, P4, and P5 families are all software compatible, enabling easy migration across a range of applications, from mid-range mixed control-data plane applications on the P3041, to high-end data plane on the P4080, to high-end control plane with the P5020.
The P3041 also integrate new IP to deliver improved functionality for mixed control/data plane applications. SATA 2.0 controllers allow connection of hard drives for applications that need to store data onboard the system, and improved Serial RapidIO controllers (v1.3 + 2.0) allow enhanced Type 9 and 11 messaging for base stations and defense applications. Dual high-speed USB 2.0 with integrated PHYs also help to reduce overall BOM cost and board space.
QorIQ P3 Communications Platforms Features
- Quad e500mc Power Architecture cores scaling to 1.5GHz frequency
- 3-level cache hierarchy with 128kB backside L2 per core and 1MB shared L3
- Hardware hypervisor
- CoreNet switch fabric
- Memory controller: DDR3/3L SDRAM up to 1.3GHz, 32/64 bit data bus w/ECC
- XAUI + 5x Gigabit Ethernet including RGMII, SGMII and 2.5Gb/s SGMII
- Up to 4 PCI Express 2.0 to 5GHz
- Dual SRIO (1.3 + 2.0) to 5GHz
- Dual SATA 2.0
- Dual USB with integrated PHY
- High-speed Aurora debug port
- Power: less than 12W typical
