Ask a power converter designer what they want from a semiconductor switch and the answer might be something like: “Low on-resistance, high off-resistance, and the fastest possible transition between the two states”. The idea of course, is that simplistically, this gives low power dissipation. SiC FETs come close to this ideal, with on-resistance now less than 6 milliohms in the 750 V class, and edge rates that are in the nanosecond region, promising efficiency figures of 99.5% plus for converters and inverters in the multi-kW range.
Given a little thought, the designer will also throw in a few ‘by the ways’ such as easy gate drive, high voltage rating, efficient third quadrant operation, high avalanche energy and short-circuit rating, low thermal resistance, low system cost and probably a few more. Fortunately, SiC FETs have these bases covered as well, with figures of merit that are best-in-class.
So, we have a happy designer, until they let a SiC FET loose in a breadboard at maximum edge rates, and there is instant smoke. “The supply voltage was well below the maximum and there was only light load!” But with how much wiring and connection inductance? That phenomenal current edge rate of 3000 A/µs with just 100 nH of inductance produced a voltage spike of 300 V from our familiar equation
stressing the switch, and provoking a high frequency ring lasting microseconds that wiped out local radio reception, for the short period before the SiC FET succumbed.
We now realize that unless we work towards zero connection inductance or wildly over-specify the switch voltage rating and allow for heavy EMI filtering, edge rates need to be controlled and ringing damped. The traditional way to limit the voltage spike has been to add series gate resistance RG(OFF), but this has its own problems, adding a delay to the waveforms that limits duty cycle and high frequency operation – one of the headline advantages of a wide band-gap switch. A gate resistor also substantially increases switch losses and has little effect on the ringing.
A better solution is a simple RC snubber. You might baulk at the idea of the large, hot resistor-capacitor network typically needed with IGBTs, but for SiC FETs, its different. It is used mainly to damp the resonance between connection inductance and device capacitance, which is extremely low with SiC FETs. This means that a capacitance of around 200 pF (2X or 3X of COSS(ER)) is all that is typically needed with a few ohms of series resistance to provide the damping. Some power is dissipated in the snubber resistor but the network acts to reduce overlap between switch-off voltage and current in both hard and soft-switched applications, so losses are actually less on this transition.
A snubber produces some dissipation on turn-on, so for a complete picture, total losses EON + EOFF should be considered. The Figure 1 shows ETOTAL for a 40-milliohm. The blue line is with no snubber and 5 ohms for both RG(ON) and RG(OFF). The orange line is with 5 ohms for RG(ON), zero ohms for RG(OFF) and with a 200 pF/10 ohms snubber. There is an obvious net benefit using the snubber at 40 A, of about 10.9 W reduced dissipation when operating at 40 kHz. At light loads the situation is reversed but dissipation is low at these levels.
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| Figure 1. | The total losses vs. drain current. |
A snubber is a great solution but is it an inconvenient overhead? If energy absorbed by a snubber resistor is evaluated in a typical application, it could be around 120 µJ per cycle, equating to over 5 W at 40 kHz. However, tests show that most of this is dissipated in the SiC FET channel as it transitions through its linear region at turn-on, rather than in the snubber resistor. The result is that a 1 W resistor is typically adequate in the snubber, which could easily be a surface mount type at this power level. The capacitor is small.
The designer can now happily tick off another item in their wish list for a perfect switch – a device that can be easily and cheaply tamed to reduce overshoots and ringing, without compromising other benefits.
