Additional peaking caused by parasitic capacitance
| Authors | John Ardizzoni - Analog Dialogue |
| Main Document | Article «A Practical Guide to High-Speed Printed-Circuit-Board Layout. Part 1» |
| Description | Figure 4 |
| File Format / Size | PDF / 11 Kb |
| Document Language | English |
Other Materials from the Main Document
- Article «A Practical Guide to High-Speed Printed-Circuit-Board Layout. Part 1»
- Figure 1. Capacitor impedance vs. frequency
- Figure 2. Parallel-capacitor rails-to-ground bypassing
- Figure 3. Typical op amp circuit, as designed (a) and with parasitics (b)
- Figure 4. Additional peaking caused by parasitic capacitance
- Figure 5. Capacitance between two plates
- Figure 6. Inductance of a trace length
- Figure 7. Pulse response with - and without - ground plane
- Figure 8. Via dimensions
