12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (Cypress) - 2
| Manufacturer | Cypress |
| Description | The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2's complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps |
| Pages / Page | 23 / 2 — Functional Description |
| File Format / Size | PDF / 394 Kb |
| Document Language | English |
Functional Description
Text Version of Document
12-Bit Incremental ADC For example, when Vin = +Vref, there are 249 CPU cycles (maximum 13 bit). When Vin = AGND, there are 47 CPU cycles (average 13 bit). When Vin = -Vref, there are 43 CPU cycles (minimum 7-13 bit). Figure 1. ADCINC12 Block Diagram
Functional Description
The ACDINC12 User Module is formed from a single analog switched capacitor PSoC block and two digital PSoC blocks, as shown in Figure 2. Figure 2. Simplified Schematic of the ADCINC12 The analog block is configured as a integrator that can be reset. Depending on the output polarity, the reference control is configured so that the reference voltage is either added or subtracted from the input and placed in the integrator. This reference control attempts to pull the integrator output back towards AGND. If the integrator is operated 4096 (212) times and the output voltage comparator is positive “n" of those times, the residual voltage (Vresid) at the output is: Document Number: 001-13252 Rev. *H Page 2 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
Functional Description
The ACDINC12 User Module is formed from a single analog switched capacitor PSoC block and two digital PSoC blocks, as shown in Figure 2. Figure 2. Simplified Schematic of the ADCINC12 The analog block is configured as a integrator that can be reset. Depending on the output polarity, the reference control is configured so that the reference voltage is either added or subtracted from the input and placed in the integrator. This reference control attempts to pull the integrator output back towards AGND. If the integrator is operated 4096 (212) times and the output voltage comparator is positive “n" of those times, the residual voltage (Vresid) at the output is: Document Number: 001-13252 Rev. *H Page 2 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
