12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (Cypress) - 6
| Manufacturer | Cypress |
| Description | The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2's complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps |
| Pages / Page | 23 / 6 — Parameter. Typical. Limit. Units. Conditions and Notes |
| File Format / Size | PDF / 394 Kb |
| Document Language | English |
Parameter. Typical. Limit. Units. Conditions and Notes
Text Version of Document
12-Bit Incremental ADC
Parameter Typical Limit Units Conditions and Notes
Offset Error 9 -- mV Gain Error Including Reference Gain Error 1.5 -- % FSR Excluding Reference Gain Error2 0.1 -- % FSR Operating Current Low Power 250 -- µA Med Power 640 -- µA High Power 2000 -- µA Data Clock -- 0.125 to 8.0 MHz Input to digital blocks and analog column clock The following values are indicative of expected performance and based on initial characterization data. Unless otherwise specified in the following table, TA = 25°C, Vdd = 3.3V, Power HIGH, OpAmp bias LOW, output referenced to 1.64V external Analog Ground on P2[4] with 1.25 external Vref on P2[6], sample rates of 100 sps, and a data clock of 1.66 MHz, unless otherwise noted. Table 2. 3.3V ADCINC12 DC and AC Electrical Characteristics for PSoC Devices
Parameter Typical Limit Units Conditions and Notes
Input Input Voltage Range --- Vss to Vdd Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance1 3 -- pF Input Impedance 1/(C*Clk) -- Ω Resolution -- 12 Bits Sample Rate -- 7.8 to 480 sps SNR 72 -- dB DC Accuracy INL 1.0 -- LSB DNL 0.5 -- LSB Offset Error 7 -- mV Gain Error Including Ref Gain Error 1.5 -- % FSR Excluding Reference Gain Error2 0.4 -- % FSR Operating Current Document Number: 001-13252 Rev. *H Page 6 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
Parameter Typical Limit Units Conditions and Notes
Offset Error 9 -- mV Gain Error Including Reference Gain Error 1.5 -- % FSR Excluding Reference Gain Error2 0.1 -- % FSR Operating Current Low Power 250 -- µA Med Power 640 -- µA High Power 2000 -- µA Data Clock -- 0.125 to 8.0 MHz Input to digital blocks and analog column clock The following values are indicative of expected performance and based on initial characterization data. Unless otherwise specified in the following table, TA = 25°C, Vdd = 3.3V, Power HIGH, OpAmp bias LOW, output referenced to 1.64V external Analog Ground on P2[4] with 1.25 external Vref on P2[6], sample rates of 100 sps, and a data clock of 1.66 MHz, unless otherwise noted. Table 2. 3.3V ADCINC12 DC and AC Electrical Characteristics for PSoC Devices
Parameter Typical Limit Units Conditions and Notes
Input Input Voltage Range --- Vss to Vdd Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance1 3 -- pF Input Impedance 1/(C*Clk) -- Ω Resolution -- 12 Bits Sample Rate -- 7.8 to 480 sps SNR 72 -- dB DC Accuracy INL 1.0 -- LSB DNL 0.5 -- LSB Offset Error 7 -- mV Gain Error Including Ref Gain Error 1.5 -- % FSR Excluding Reference Gain Error2 0.4 -- % FSR Operating Current Document Number: 001-13252 Rev. *H Page 6 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
