12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (Cypress) - 9
| Manufacturer | Cypress |
| Description | The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2's complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps |
| Pages / Page | 23 / 9 — Parameter. Typical1. Limit. Units. Conditions and Notes |
| File Format / Size | PDF / 394 Kb |
| Document Language | English |
Parameter. Typical1. Limit. Units. Conditions and Notes
Text Version of Document
12-Bit Incremental ADC Table 5. 3.3V ADCINC12 DC and AC Electrical Characteristics
Parameter Typical1 Limit Units Conditions and Notes
INPUT Input Voltage Range2 --- Vss to Vdd Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance3 0.8 -- pF Input Impedance4,5 1/(C*Clk) -- W Resolution -- 12 Bits 2’s Complement Sample Rate -- 7.8 to 100 sps samples per second SNR6 68 dB at 100 sps DC ACCURACY INL 0.5 1 LSB DNL 0.25 0.5 LSB Offset Error 12 49 mV Gain Error 0.5 1.5 % FSR Relative to reference input OPERATING CURRENT Low Power 70 -- µA Med Power 170 -- µA High Power 540 970 µA Data Clock7 -- 0.125 to 1.66 MHz Input to digital blocks and analog column clock Electrical Characteristics Notes
1.
Typical values represent parametric norm at +25°C.
2.
Input voltages above the maximum generate a maximum positive reading. Input voltages below the minimum generate a maximum negative reading.
3.
User module only, not including I/O pin.
4.
The input capacitance or impedance is only applicable when input to analog block is directly to a pin.
5.
C = input capacitance, clk = Data Clock (Analog Column Clock).
6.
SNR = Ratio of power of full-scale, single tone divided by total noise integrated to Fsample/2.
7.
Minimum data clock is 125 kHz when the CPU is operating at 12 MHz or lower. If the CPU is operating at 24 MHz, the minimum data clock is 250 kHz. Document Number: 001-13252 Rev. *H Page 9 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
Parameter Typical1 Limit Units Conditions and Notes
INPUT Input Voltage Range2 --- Vss to Vdd Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance3 0.8 -- pF Input Impedance4,5 1/(C*Clk) -- W Resolution -- 12 Bits 2’s Complement Sample Rate -- 7.8 to 100 sps samples per second SNR6 68 dB at 100 sps DC ACCURACY INL 0.5 1 LSB DNL 0.25 0.5 LSB Offset Error 12 49 mV Gain Error 0.5 1.5 % FSR Relative to reference input OPERATING CURRENT Low Power 70 -- µA Med Power 170 -- µA High Power 540 970 µA Data Clock7 -- 0.125 to 1.66 MHz Input to digital blocks and analog column clock Electrical Characteristics Notes
1.
Typical values represent parametric norm at +25°C.
2.
Input voltages above the maximum generate a maximum positive reading. Input voltages below the minimum generate a maximum negative reading.
3.
User module only, not including I/O pin.
4.
The input capacitance or impedance is only applicable when input to analog block is directly to a pin.
5.
C = input capacitance, clk = Data Clock (Analog Column Clock).
6.
SNR = Ratio of power of full-scale, single tone divided by total noise integrated to Fsample/2.
7.
Minimum data clock is 125 kHz when the CPU is operating at 12 MHz or lower. If the CPU is operating at 24 MHz, the minimum data clock is 250 kHz. Document Number: 001-13252 Rev. *H Page 9 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
