12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (Cypress) - 8
| Manufacturer | Cypress |
| Description | The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2's complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps |
| Pages / Page | 23 / 8 — Parameter. Typical1. Limit. Units. Conditions and Notes |
| File Format / Size | PDF / 394 Kb |
| Document Language | English |
Parameter. Typical1. Limit. Units. Conditions and Notes
Text Version of Document
12-Bit Incremental ADC Unless otherwise specified in the following table, all limits guaranteed for TA = -40°C to +85°C, Vdd = 4.75V to 5.5V, Power HIGH, Op-Amp bias LOW, output referenced to 2.5V external Analog Ground on P2[4] with 1.25 external Vref on P2[6], sample rates of 100 sps, and a data clock of 1.66 MHz, unless otherwise noted. Table 4. 5.0V ADCINC12 DC and AC Electrical Characteristics
Parameter Typical1 Limit Units Conditions and Notes
INPUT Input Voltage Range2 --- Vss to Vdd Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance3 0.8 -- pF Input Impedance4,5 1/(C*Clk) -- W Resolution -- 12 Bits 2’s Complement Sample Rate -- 7.8 to 100 sps samples per second SNR6 68 dB at 100 sps DC ACCURACY INL 0.5 1 LSB DNL 0.25 0.5 LSB Offset Error 12 49 mV Using external AGND Gain Error 0.5 1.5 % FSR Relative to reference input OPERATING CURRENT Low Power 125 -- µA Med Power 240 -- µA High Power 640 1060 µA Data Clock7 -- 0.125 to 1.66 MHz Input to digital blocks and analog column clock Unless otherwise specified in the following table, all limits guaranteed for TA = -40°C to +85°C, Vdd = 3.3V to 0.3V, Power HIGH, OpAmp bias LOW, output referenced to 1.64V external Analog Ground on P2[4] with 1.25 external Vref on P2[6], sample rates of 100 sps, and a data clock of 1.66 MHz, unless otherwise noted. Document Number: 001-13252 Rev. *H Page 8 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
Parameter Typical1 Limit Units Conditions and Notes
INPUT Input Voltage Range2 --- Vss to Vdd Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance3 0.8 -- pF Input Impedance4,5 1/(C*Clk) -- W Resolution -- 12 Bits 2’s Complement Sample Rate -- 7.8 to 100 sps samples per second SNR6 68 dB at 100 sps DC ACCURACY INL 0.5 1 LSB DNL 0.25 0.5 LSB Offset Error 12 49 mV Using external AGND Gain Error 0.5 1.5 % FSR Relative to reference input OPERATING CURRENT Low Power 125 -- µA Med Power 240 -- µA High Power 640 1060 µA Data Clock7 -- 0.125 to 1.66 MHz Input to digital blocks and analog column clock Unless otherwise specified in the following table, all limits guaranteed for TA = -40°C to +85°C, Vdd = 3.3V to 0.3V, Power HIGH, OpAmp bias LOW, output referenced to 1.64V external Analog Ground on P2[4] with 1.25 external Vref on P2[6], sample rates of 100 sps, and a data clock of 1.66 MHz, unless otherwise noted. Document Number: 001-13252 Rev. *H Page 8 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
